Figure 351. Master And Three Independent Slaves - STMicroelectronics STM32WL5 Series Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
Rx shift register
Tx shift register
1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to
prevent any MODF error.
2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see I/O alternate function input/output section (GPIO)).
37.5.4 Multimaster communication
Unless SPI bus is not designed for a multimaster capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.
1260/1450

Figure 351. Master and three independent slaves

SPI clock
generator
Master
(1)
NSS
MISO
MOSI MOSI
SCK
IO1
IO2
IO3
MISO
MOSI
RM0453 Rev 5
MISO
Tx shift register
Rx shift register
SCK
NSS
Slave 1
MISO
Tx shift register
MOSI
Rx shift register
SCK
NSS
Slave 2
Tx shift register
Rx shift register
SCK
NSS
Slave 3
RM0453
MSv39626V1