STMicroelectronics STM32WL5 Series Reference Manual page 323

RM0453
Bit 19 HSEMRST: HSEM reset
Bit 18 RNGRST: True RNG reset
Bit 17 AESRST: AES hardware accelerator reset
Bit 16 PKARST: PKA hardware accelerator reset
Bits 15:0 Reserved, must be kept at reset value.
7.4.11 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x038
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
LPTIM1 DAC
Res. Res.
RST RST
rw rw
15 14 13
SPI2S2
Res. Res. Res.
RST
rw
Bit 31 LPTIM1RST: Low-power timer 1 reset
Bit 30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC reset
Bits 28:24 Reserved, must be kept at reset value.
This bit is set and cleared by software.
0: No effect
1: HSEM reset
This bit is set and cleared by software.
0: No effect
1: True RNG reset
This bit is set and cleared by software.
0: No effect
1: AES reset
This bit is set and cleared by software. PKA reset is disabled when a hardware PKA SRAM
erase is ongoing.
0: No effect
1: PKA reset
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set and cleared by software.
0: No effect
1: LPTIM1 reset
This bit is set and cleared by software.
0: No effect
1: DAC reset
24 23 22 21
I2C3 I2C2 I2C1
Res.
RST RST RST
rw rw rw
8 7 6
Res. Res. Res. Res.
RM0453 Rev 5
Reset and clock control (RCC)
20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. Res.
17 16
USART2
Res.
RST
rw
1 0
TIM2
Res.
RST
rw
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