Table of Contents
Advertisement
RM0453
Bit 10 Reserved, must be kept at reset value.
Bit 9 ADCSMEN: ADC clocks enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: ADC bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: ADC bus clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bits 8:0 Reserved, must be kept at reset value.
7.4.28
RCC APB3 peripheral clock enable in Sleep mode register
(RCC_APB3SMENR)
Address offset: 0x084
Reset value: 0x0000 0001
Access: word, half-word and byte access
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SUBGHZSPISMEN: Sub-GHz radio SPI clock enable during CPU1 CSleep and CStop modes
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software.
0: Sub-GHz radio SPI clock disabled by the clock gating during CPU1 CSleep and CStop
modes
1: Sub-GHz radio SPI clock enabled by the clock gating during CPU1 CSleep mode,
disabled during CPU1 CStop mode
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
Reset and clock control (RCC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
rw
341/1450
371
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers