Figure 342. Hardware Flow Control Between 2 Lpuarts; Figure 343. Rs232 Rts Flow Control - STMicroelectronics STM32WL5 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
enable bit (EIE bit in the LPUART_CR3 register), which, if set, enables an interrupt after the
current byte if any of these errors occur.
36.4.13 RS232 Hardware flow control and RS485 Driver Enable
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The
RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the LPUART_CR3 register).
RS232 RTS flow control
If the RTS flow control is enabled (RTSE = 1), then RTS is deasserted (tied low) as long as
the LPUART receiver is ready to receive a new data. When the receive register is full, RTS
is asserted, indicating that the transmission is expected to stop at the end of the current
frame. Figure 343
RX
RTS
Note: When FIFO mode is enabled, RTS is asserted only when RXFIFO is full.
1222/1450
Figure 328 shows how to connect 2 devices in this mode:

Figure 342. Hardware flow control between 2 LPUARTs

LPUART 1
TX
TX circuit
CTS
RX
RX circuit
RTS
shows an example of communication with RTS flow control enabled.

Figure 343. RS232 RTS flow control

Start
Data 1
bit
RM0453 Rev 5
RX
RTS
TX
CTS
Stop Start
Idle
bit bit
RXNE Data 1 read
Data 2 can now be transmitted
RM0453
LPUART 2
RX circuit
TX circuit
MSv31892V2
Stop
Data 2
bit
RXNE
MSv68794V1