Figure 278. Setup And Hold Timings - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
When the SCL falling edge is internally detected, a delay (
) is inserted before sending SDA output:
t
HD;DAT
t = (PRESC + 1) x t
PRESC
The total SDA output delay is:
t + {[SDADEL x (PRESC + 1) + 1] x t
SYNC1
duration depends upon:
t
SYNC1
–
–
–
–
To bridge the undefined region of the SCL falling edge, the user must program SDADEL in
such a way that:
{t + t
f (max)
SDADEL ≤ {t

Figure 278. Setup and hold timings

SCL falling edge internal
SCL falling edge internal
detection
detection
SCL
SCL
SDA
SDA
Data hold time: in case of transmission, the data is sent on SDA output after
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.
the SDADEL delay, if it is already available in I2C_TXDR.
SCL
SCL
SDA
SDA
Data setup time: in case of transmission, the SCLDEL counter starts
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output.
when the data is sent on SDA output.
.
I2CCLK
SCL falling slope
When enabled, input delay brought by the analog filter: t
When enabled, input delay brought by the digital filter: t
Delay due to SCL synchronization to I2CCLK clock (two to three I2CCLK periods)
- t - [(DNF + 3) x t
HD;DAT (min)
AF(min)
- t
HD;DAT (max)
AF(max)
Inter-integrated circuit (I2C) interface
DATA HOLD TIME
DATA HOLD TIME
t
t
SDADEL: SCL stretched low by the I2C
SDADEL: SCL stretched low by the I2C
SYNC1
SYNC1
SDA output delay
SDA output delay
t
t
HD;DAT
HD;DAT
DATA SETUP TIME
DATA SETUP TIME
SCLDEL
SCLDEL
SCL stretched low by the I2C
SCL stretched low by the I2C
t
t
SU;STA
SU;DAT
t
SDADEL
I2CCLK}
]} / {(PRESC + 1) x t
I2CCLK
- [(DNF + 4) x t
I2CCLK
RM0453 Rev 5
, impacting the hold time
t
SDADEL
= SDADEL x t + t
PRESC I2CCLK
< t
AF(min) AF
= DNF
x
DNF
I2CCLK
]} / {(PRESC + 1) x t
I2CCLK
MSv40108V1
MS49608V1
, where
< t
AF(max)
t
I2CCLK
} ≤ SDADEL
}
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