STMicroelectronics STM32WL5 Series Reference Manual page 644

True random number generator (RNG)
Bit 5 CED: Clock error detection
Bit 4 Reserved, must be kept at reset value.
Bit 3 IE: Interrupt enable
Bit 2 RNGEN: True random number generator enable
Bits 1:0 Reserved, must be kept at reset value.
22.7.2 RNG status register (RNG_SR)
Address offset: 0x004
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 SEIS: Seed error interrupt status
Bit 5 CEIS: Clock error interrupt status
Bits 4:3 Reserved, must be kept at reset value.
644/1450
0: Clock error detection enabled
1: Clock error detection is disabled
The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is
enabled, that is to enable or disable CED, the RNG must be disabled.
Writing this bit is taken into account only if the CONDRST bit is set to 1 in the same access,
while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK = 1.
0: RNG interrupt is disabled
1: RNG interrupt is enabled. An interrupt is pending as soon as DRDY = 1, SEIS = 1 or
CEIS = 1 in the RNG_SR register.
0: True random number generator is disabled. Analog noise sources are powered off and
logic clocked by the RNG clock is gated.
1: True random number generator is enabled.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is
used). Writing 1 has no effect.
0: No faulty sequence detected
1: At least one faulty sequence is detected. See SECS bit description for details.
An interrupt is pending if IE = 1 in the RNG_CR register.
This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect.
0: The RNG clock is correct (f
1: The RNG clock before the internal divider is detected too slow (f
An interrupt is pending if IE = 1 in the RNG_CR register.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. SEIS CEIS
rc_w0 rc_w0
> f /32)
RNGCLK HCLK
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. SECS
r
< f
RNGCLK
RM0453
17 16
Res. Res.
1 0
CECS DRDY
r r
/32)
HCLK