STMicroelectronics STM32WL5 Series Reference Manual page 227

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
Table 42. SUBGHZ register map and reset values (continued)
Offset
Register name
SUBGHZ_RNGR3
0x819
Reset value
SUBGHZ_RNGR2
0x81A
Reset value
SUBGHZ_RNGR1
0x81B
Reset value
SUBGHZ_RNGR0
0x81C
Reset value
SUBGHZ_AGCRSSIC0R
0x89B
Reset value
0x820-
Reserved
0x8AB
SUBGHZ_RXGAINCR
0x8AC
Reset value
0x8B0-
Reserved
0x8E6
SUBGHZ_PAOCPR
0x8E7
Reset value
0x8E8 -
Reserved
0x910
SUBGHZ_HSEINTRIMR
0x911
Reset value
SUBGHZ_HSEOUTTRIMR
0x912
Reset value
0x913-
Reserved
0x915
SUBGHZ_SMPSC0R
0x916
Reset value
0x917-
Reserved
0x919
SUBGHZ_PCR
0x91A
Reset value
0x91B-
Reserved
0x920
SUBGHZ_REGDRVTSTR
0x91F
Reset value
SUBGHZ_SMPSC2R
0x923
Reset value
Refer to
7
6
0
0
0
0
Res.
MODE
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLKDE
Res.
CLE
Res.
Res.
Res.
Res.
Section 2.6
for the register boundary addresses.
5
4
RNDATA[31:24]
0
0
0
RNDATA[23:16]
0
0
0
RNDATA[15:8]
0
0
0
RNDATA[7:0]
0
0
0
MC
0
0
0
Reserved
SENSI_ADJUST[5:0].
0
0
1
Reserved
0
1
Reserved
0
1
0
1
Reserved
Res.
Res.
0
Reserved
CLV[1:0]
1
0
1
Reserved
Res.
Res.
Res.
Res.
RM0453 Rev 5
Sub-GHz radio (SUBGHZ)
3
2
0
0
0
0
0
0
0
0
LENGTH[2:0]
0
0
0
1
OCP[5:0]
1
0
TRIM[5:0]
0
0
TRIM[5:0]
0
0
Res.
Res.
Res.
Res.
TRIM[2:0]
1
0
Res.
DRV[1:0]
1
1
0
0
0
0
0
0
0
0
0
Res.
Res.
PMODE[1:0]
0
0
0
0
1
0
1
0
Res.
Res.
Res.
Res.
EN
0
0
Res.
1
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