Figure 145. Counter Timing Diagram, Internal Clock Divided By N; Figure 146. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow) - STMicroelectronics STM32WL5 Series Reference Manual

Advanced-control timer (TIM1)
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 146. Counter timing diagram, update event with ARPE=1 (counter underflow)

Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload active
736/1450

Figure 145. Counter timing diagram, internal clock divided by N

CK_PSC
20
(UIF)
CK_PSC
CEN
06
(UIF)
FD
register
Write a new value in TIMx_ARR
register
RM0453 Rev 5
1F
01
05 04 03 02 01 00
FD
00
01 02 03 04 05 06 07
36
36
RM0453
MS31192V1
MS31193V1