Figure 158. Output Stage Of Capture/Compare Channel (Channel 1, Idem Ch. 2 And 3); Figure 159. Output Stage Of Capture/Compare Channel (Channel 4) - STMicroelectronics STM32WL5 Series Reference Manual

RM0453

Figure 158. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)

TIMx_SMCR
OCCS
OCREF_CLR
0
ETRF
1
ocref_clr_int
OC1REF
CNT>CCR1
Output
mode
CNT=CCR1
controller
(1)
OCxREF
OC5REF
OC1CE OC1M[3:0]
TIM1_CCMR1
1. OCxREF, where x is the rank of the complementary channel
TIMx_SMCR
OCREF_CLR
ETRF
ocref_clr_int
CNT > CCR4
CNT = CCR4
To the master mode
controller
OC1REFC
Output Dead-time
selector generator
DTG[7:0]
TIM1_BDTR

Figure 159. Output stage of capture/compare channel (channel 4)

OCCS
0
1
OC4REF
Output
mode
selector
controller
OC3REF
OC4CE OC4M[3:0]
TIM1_CCMR2
'0'
x0
01
OC1_DT
11
OC1N_DT
11
10
'0'
0x
CC1NE CC1E
TIM1_CCER
To the master
mode controller
OC4REFC
'0'
0
Output
1
CC4E
TIM1_CCER
RM0453 Rev 5
Advanced-control timer (TIM1)
0
Output
enable
1
circuit
CC1P
TIM1_CCER
0
Output
enable
1
circuit
CC1E TIM1_CCER
CC1NE
MOE OSSI OSSR
CC1NP
TIM1_CCER
TIM1_BDTR
OIS1 OIS1N
TIM1_CR2
0
Output
enable
1
circuit
CC4P
CC4E TIM1_CCER
TIM1_CCER
MOE OSSI
OIS4
OC1
OC1N
MS31199V2
OC4
TIM1_BDTR
TIM1_CR2
MS33100V2
745/1450
821