Figure 264. Lptim Output Waveform, Single Counting Mode Configuration When Repetition Register Content Is Different Than Zero (With Preload = 1) - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
The external triggers are considered asynchronous signals for the LPTIM. So after a trigger
detection, a two-counter-clock period latency is needed before the timer starts running due
to the synchronization.
If a new trigger event occurs when the timer is already started it is ignored (unless timeout
function is enabled).
Note: The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these
bits when the timer is disabled is discarded by hardware.
Note: When starting the counter by software (TRIGEN[1:0] = 00), there is a delay of 3 kernel clock
cycles between the LPTIM_CR register update (set one of SNGSTRT or CNTSTRT bits)
and the effective start of the counter.
28.4.8 Operating mode
The LPTIM features two operating modes:
•
The Continuous mode: the timer is free running, the timer is started from a trigger event
and never stops until the timer is disabled
• One-shot mode: the timer is started from a trigger event and stops when an LPTIM
update event is generated.
One-shot mode
To enable the one-shot counting, the SNGSTRT bit must be set.
A new trigger event re-starts the timer. Any trigger event occurring after the counter starts
and before the next LPTIM update event, is discarded.
In case an external trigger is selected, each external trigger event arriving after the
SNGSTRT bit is set, and after the repetition counter has stopped (after the update event),
and if the repetition register content is different from zero, the repetition counter gets
reloaded with the value already contained by the repetition register and a new one-shot
counting cycle is started as shown in
Figure 264. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1)
LPTIM_RCR
Repetition counter
LPTIM_ARR
External trigger event
Ignored external trigger event
2
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0
PWM
RM0453 Rev 5
Figure 264.
2
1 0
Low-power timer (LPTIM)
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