Table 61. Peripheral Clock Enable - STMicroelectronics STM32WL5 Series Reference Manual

Reset and clock control (RCC)
7.2.21 Peripheral clocks enable
Most peripheral bus and kernel clocks can be individually enabled per CPU.The
RCC_AHBxENR and RCC_APBxENRy registers enable peripheral clocks for CPU1.
RCC_C2_AHBxENR and RCC_C2_APBxENR registers enable peripheral clocks for CPU2.
The peripheral clocks follow the CPUs state for which it is enabled and the system state
(see the table below). The RTC kernel clock is enabled by the RTCEN bit and does not
depend on the CPUs state nor the system state.
Peripheral bus clock activity during the CPU Sleep mode is controlled by the xxxxSMEN bit
of the RCC_AHBxSMENR and RCC_APBxSMENRy registers for CPU1, and
RCC_C2_AHBxSMENR and RCC_C2_APBxSMENRy registers for CPU2.The peripheral
bus clock during Sleep mode follows the CPUs state for which it is enabled (see the table
below).
xxxEN xxxSMEN
0
1
x
1. Only the I2C, LPTIM, USART, LPUART, True RNG, ADC and SPI I2S peripherals have a kernel clock
controlled by xxxEN and xxxSMEN. The RTC has a kernel clock controlled by RTCEN and does not
depend on xxxEN and xxxSMEN.
2. Only when the xxxEN bit associated with the CPU in CRun is enabled.
3. Only when both the xxxEN bit and xxxSMEN bit associated with the CPU in CSleep are enabled.
4. The RTC kernel clock when selected from LSI or LSE is still clocked in Standby mode and still clocked in
VBAT and Shutdown modes when LSE is selected.
When the peripheral bus clock is not active, read or write accesses to the peripheral
registers are not supported.
When the peripheral kernel clock is not active, the peripheral functionality is stopped.
The enable bits have a synchronization mechanism to create a glitch free clock for the
peripheral. After the enable bit is set, there is a two clock cycles delay before the clock is
active in the peripheral.
Caution: Just after enabling a clock for a peripheral, the software must wait for a delay before
accessing the peripheral registers.
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Table 61. Peripheral clock enable

CPU System
mode mode
Any Any
x
CRun Run
CSleep
0 and Run
CStop
CSleep Run
Run
1
Stop
CStop
Standby or
x
Shutdown
RM0453 Rev 5
Bus clock
Stopped
(2)
Clocked
Stopped
(3)
Clocked
Stopped
Clocked when from HSI16, LSI, or LSE
Stopped
Stopped when from bus clock, SYSCLK,
PLL clocks, or MSI clocks
Stopped
RM0453
(1)
Kernel clock
Stopped
Clocked
Clocked
Clocked
Clocked
(4)
Stopped