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Power control (PWR)
Bit 2 RFBUSYMS: Radio busy masked signal status
Bit 1 RFBUSYS: Radio busy signal status
Bit 0 C2BOOTS: CPU2 boot/wake-up request source information
6.6.7
PWR status clear register (PWR_SCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x018
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
w
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 CC2HF: Clear CPU2 hold interrupt flag
Setting this bit clears the C2HF flag in the PWR_SR1. This bit is always read 0.
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 CWRFBUSYF: Clear wake-up radio busy flag
Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0.
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 CWPVDF: Clear wake-up PVD interrupt flag
Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0.
Bits 7:3 Reserved, must be kept at reset value.
272/1450
This bit indicates the actual status of the radio busy masked signal.
0: radio busy masked signal low (not busy)
1: radio busy masked signal high (busy)
This bit indicates the actual status of the radio busy signal.
0: radio busy signal low (not busy)
1: radio busy signal high (busy)
This bit indicates the CPU2 boot/wake-up request source.
0: CPU2 booted from an illegal access event
1: CPU2 booted from a C2BOOT request
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
w
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
w
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
w
RM0453
17
16
Res.
Res.
1
0
w
w
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