STMicroelectronics STM32WL5 Series Reference Manual page 447

RM0453
Table 76. STM32WL5x peripherals interconnect matrix
Source
COMP1
COMP2
SYST ERR
1. Numbers in this table are links to corresponding subsections of
2. The "-" symbol in grayed cells means no interconnect.
12.3 Interconnection details
12.3.1 From timer (TIM1/TIM2/TIM17) to timer (TIM1/TIM2)
Purpose
Some timers are linked together internally for synchronization or chaining.
When one timer is configured in Master mode, it can reset, start, stop or clock the counter of
another timer configured in Slave mode. A description of the feature is provided in
Section 25.3.26: Timer
The synchronization modes are detailed in the following sections:
• Section 25.3.26: Timer synchronization
•
Section 26.3.18: Timers and external trigger synchronization
timers (TIM2)
Triggering signals
The output (from master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a
configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.
The input and output signals for TIM1 are shown in
block diagram.
The possible master/slave connections are given in tables below:
•
Table 179: TIM1 internal trigger connection
•
Table 183: TIM2 internal trigger connection
Active power modes
Run, Sleep, LPRun, LPSleep
10 10 10 10
10 10 10 10
11 - 11 11
synchronization.
RM0453 Rev 5
Peripherals interconnect matrix
Destination
7 7 - -
7 7 - -
- - - -
Section 12.3: Interconnection
for advanced-control timers (TIM1)
Figure 128: Advanced-control timer
for TIM1
for TIM2
(1) (2)
(continued)
- - - -
- - - -
- - - -
details.
for general-purpose
- -
- -
- -
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