Figure 299. Timeout Intervals For T Low:sext , T Low:mext - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
SMBCLK
SMBDAT
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have
been high for t
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.
34.4.12 SMBus initialization
This section is relevant only when SMBus feature is supported (see
In addition to I2C initialization, some other specific initialization must be done to perform
SMBus communication.
Received command and data acknowledge control (slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave byte control mode must be enabled by setting the
SBC bit in the I2C_CR1 register. Refer to
Specific address (slave mode)
The specific SMBus addresses must be enabled if needed. Refer to
more details.
•
The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
•
The alert response address (0b0001100) is enabled by setting the ALERTEN bit in the
I2C_CR1 register.
1084/1450
Figure 299. Timeout intervals for t
Start
t
LOW:MEXT
greater than t
IDLE ,
HIGH
RM0453 Rev 5
LOW:SEXT
t
LOW:SEXT
Clk
Ack
t
LOW:MEXT
(refer to Table 226).
MAX
Slave byte control mode
, t .
LOW:MEXT
Stop
Clk
Ack
t
LOW:MEXT
MS19866V1
Section 34.3).
for more details.
Bus idle detection
RM0453
for