STMicroelectronics STM32WL5 Series Reference Manual page 440

System configuration controller (SYSCFG)
11.2.10 SYSCFG SRAM2 key register (SYSCFG_SKR)
Address offset: 0x024
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase
The following steps are required to unlock the write protection of the SRAM2ER bit in the
SYSCFG_SCSR register.
1. Write 0xCA into Key[7:0].
2. Write 0x53 into Key[7:0].
Writing a wrong key reactivates the write protection.
11.2.11 SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)
Address offset: 0x100
Reset value: 0x0000 0000
31 30 29
EXTI15 EXTI14 EXTI13 EXTI12
IM IM IM
rw rw rw
15 14 13
Res. Res. Res. Res.
Bits 31:21 EXTIxIM: EXTIx interrupt mask to CPU1 (x = 15 to 5)
0: EXTIx interrupt forwarded to CPU1
1. EXTIx interrupt to CPU1 masked
Bits 20:3 Reserved, must be kept at reset value.
Bit 2 RTCSSRUIM: RTC SSRU interrupt mask to CPU1
0: RTC SSRU interrupt forwarded to CPU1
1. RTC SSRU interrupt to CPU1 masked
Bit 1 Reserved, must be kept at reset value.
Bit 0 RTCSTAMPTAMPLSECSSIM: RTCSTAMPTAMPLSECSS interrupt mask to CPU1
0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU1
1. RTCSTAMPTAMPLSECSS interrupt to CPU1 masked
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
28 27 26 25
EXTI11I EXTI10 EXTI9I
IM M IM M
rw rw rw rw
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res.
w w
24 23 22
EXTI8I EXTI7I EXTI6I EXTI5I
M M M
rw rw rw
8 7 6
Res. Res. Res.
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
KEY[7:0]
w w w w
21 20 19 18
Res. Res. Res.
M
rw
5 4 3 2
RTCSS
Res. Res. Res.
RUIM
rw
RM0453
17 16
Res. Res.
1 0
w w
17 16
Res. Res.
1 0
RTCST
AMPTA
Res.
MPLSE
CSSIM
rw