Table 176. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs; Figure 173. Pwm Output State Following Brk And Brk2 Pins Assertion (Ossi=1) - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
The two break inputs have different behaviors on timer outputs:
–
–
The BRK has a higher priority than BRK2 input, as described in
Note: BRK2 must only be used with OSSR = OSSI = 1.
BRK
Active
Inactive
Figure 173
BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP =
CCxNP = 0 in TIMx_CCER register).

Figure 173. PWM output state following BRK and BRK2 pins assertion (OSSI=1)

BRK2
BRK
OCx
I/O state
The BRK input can either disable (inactive state) or force the PWM outputs to a
predefined safe state.
BRK2 can only disable (inactive state) the PWM outputs.

Table 176. Behavior of timer outputs versus BRK/BRK2 inputs

Timer outputs
BRK2
– Inactive then
forced output
state (after a
deadtime)
X
– Outputs disabled
if OSSI = 0
(control taken
over by GPIO
logic)
Active
gives an example of OCx and OCxN output behavior in case of active signals on
Deadtime
Active Inactive
OCxN output
state
(low side switches)
ON after deadtime
insertion
Inactive
RM0453 Rev 5
Advanced-control timer (TIM1)
Table 176.
Typical use case
OCx output
(high side switches)
OFF
Deadtime
Idle
OFF
OFF
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