Figure 137. Counter Timing Diagram, Internal Clock Divided By 1; Figure 138. Counter Timing Diagram, Internal Clock Divided By 2 - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 137. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
05
(UIF)

Figure 138. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0002
(UIF)
RM0453 Rev 5
04
03 02 01 00 36
0000
0001
Advanced-control timer (TIM1)
35 34 33 32
31
0036 0035 0034
30 2F
MS31184V1
0033
MS31185V1
731/1450
821