Sub-Ghz Radio Smps Control 0 Register (Subghz_Smpsc0R); Sub-Ghz Radio Power Control Register (Subghz_Pcr) - STMicroelectronics STM32WL5 Series Reference Manual

Sub-GHz radio (SUBGHZ)
5.10.57

Sub-GHz radio SMPS control 0 register (SUBGHZ_SMPSC0R)

Address offset: 0x916
Reset value: 0x00
7 6
Res. CLKDE
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 CLKDE: SMPS clock detection enable
Bits 5:0 Reserved, must be kept at reset value.
5.10.58

Sub-GHz radio power control register (SUBGHZ_PCR)

Address offset: 0x91A
Reset value: 0x50
This register is retained in Sleep mode but lost in Deep-Sleep mode.
7 6
Res. CLE
rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 CLE: Power-supply current limiter enable
Bits 5:4 CLV[1:0]: Power-supply current limiter value
Bits 3:0 Reserved, must be kept at reset value.
224/1450
5
Res.
SMPS clock detection must be enabled before enabling the SMPS, if the application uses an
external HSE clock source (not coming from XO or TCXO but from another device).
0: SMPS clock detection disabled
1: SMPS clock detection enabled
5
CLV[1:0]
rw
0: power-supply current limiter disabled (unlimited current)
1: power-supply current limiter enabled (current limited according to CLV[1:0])
When the power-supply current limiter is enabled by CLEN, these bits define the maximum
current limiting level.
0x0: power-supply current limiting level 25 mA
0x1: power-supply current limiting level 50 mA (default)
0x2: power-supply current limiting level 100 mA
0x3: power-supply current limiting level 200 mA
4 3
Res. Res.
4 3
Res.
rw
RM0453 Rev 5
2 1
Res. Res.
2 1
Res. Res.
RM0453
0
Res.
0
Res.