STMicroelectronics STM32WL5 Series Reference Manual page 759

RM0453
The output enable signal and output levels during break are depending on several control
bits:
–
–
–
When exiting from reset, the break circuit is disabled and the MOE bit is low. The break
functions can be enabled by setting the BKE and BK2E bits in the TIMx_BDTR register. The
break input polarities can be selected by configuring the BKP and BK2P bits in the same
register. BKE/BK2E and BKP/BK2P can be modified at the same time. When the BKE/BK2E
and BKP/BK2P bits are written, a delay of 1 APB clock cycle is applied before the writing is
effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the
bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if MOE is set to 1 whereas it was low, a delay
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
The break can be generated from multiple sources which can be individually enabled and
with programmable edge sensitivity, using the TIMx_AF1 and TIMx_AF2 registers.
The sources for break (BRK) channel are:
•
An external source connected to one of the BKIN pin (as per selection done in the
SYSCFG_CFGR2 register), with polarity selection and optional digital filtering
•
An internal source:
–
–
–
–
–
–
The sources for break2 (BRK2) are:
•
An external source connected to one of the BKIN pin (as per selection done in the
SYSCFG_CFGR2 register), with polarity selection and optional digital filtering
•
An internal source coming from a comparator output.
Break events can also be generated by software using BG and B2G bits in the TIMx_EGR
register. The software break generation using BG and B2G is active whatever the BKE and
BK2E enable bits values.
the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by
software and is reset in case of break or break2 event.
the OSSI bit in the TIMx_BDTR register defines whether the timer controls the
output in inactive state or releases the control to the GPIO controller (typically to
have it in Hi-Z mode)
the OISx and OISxN bits in the TIMx_CR2 register which are setting the output
shut-down level, either active or inactive. The OCx and OCxN outputs cannot be
set both to active level at a given time, whatever the OISx and OISxN values.
Refer to Table 180: Output control bits for complementary OCx and OCxN
channels with break feature on page 802
®
the Cortex -M4 LOCKUP output
the PVD output
the SRAM parity error signal
a flash memory ECC double error detection
a clock failure event generated by the CSS detector
the output from a comparator, with polarity selection and optional digital filtering
for more details.
RM0453 Rev 5
Advanced-control timer (TIM1)
759/1450
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