Figure 393. Cpu2 Coresight Topology - STMicroelectronics STM32WL5 Series Reference Manual

Debug support (DBG)
The topology for the CoreSight components in the CPU2 subsystem is shown in
AP1
(AHB-AP)
0xF0000000
AP_BASER register
(0xF8)
38.13.1 CPU2 ROM1 memory type register (C2ROM1_MEMTYPER)
Address offset: 0xFCC
Reset value: 0x0000 0001
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SYSMEM: system memory
1: System memory present on this bus
1416/1450

Figure 393. CPU2 CoreSight topology

CPU2 ROM1 table
@0xF0000000
0x000 Offset: 0xF00FF000
0x004 Offset: 0x00001000
0x008 Offset: 0x00002000
0x00C Offset: 0x10000000
0x008 Top of table
0xFD0 PIDR4
0xFFC CIDR3
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
CPU2 ROM2 table
@0xE00FF000
0x000 Offset: 0xFFF0F000
0x004 Offset: 0xFFF02000
0x008 Offset: 0xFFF03000
0x00C Top of table
0xFD0 PIDR4
0xFFC CIDR3
Cross trigger interface (CTI)
@0xF0001000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
RM0453 Rev 5
Figure
System control space (SCS)
@0xE000E000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
Data watchpoint/trace (DWT)
@0xE0001000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
Breakpoint Unit (BPU)
@0xE0002000
0x000 Register file base
0xFD0 PIDR4
0xFFC CIDR3
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. Res. Res. Res.
RM0453
393.
MSv60372V1
16
Res.
0
SYSMEM
r