STMicroelectronics STM32WL5 Series Reference Manual page 597

RM0453
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DOR1 register has been loaded with the
DAC_DHR1 register contents.
Note: TSEL1[3:0] bit cannot be changed when the EN1 bit is set.
When software trigger is selected, the transfer from the DAC_DHR1 register to the
DAC_DOR1 register takes only one dac_pclk clock cycle.
19.4.8 DMA requests
The DAC channel has a DMA capability. One DMA channel is used to service DAC channel
DMA request.
When an external trigger (but not a software trigger) occurs while the DMAEN1 bit is set, the
value of the DAC_DHR1 register is transferred into the DAC_DOR1 register when the
transfer is complete, and a DMA request is generated.
As DAC_DHR1 to DAC_DOR1 data transfer occurred before the DMA request, the very first
data has to be written to the DAC_DHR1 before the first trigger event occurs.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channel1 underrun flag DMAUDR1 in the DAC_SR register is set,
reporting the error condition. The DAC channel1 continues to convert old data.
The software must clear the DMAUDR1 flag by writing 1, clear the DMAEN bit of the used
DMA stream and re-initialize both DMA and DAC channel1 to restart the transfer correctly.
The software must modify the DAC trigger conversion frequency or lighten the DMA
workload to avoid a new DMA underrun. Finally, the DAC conversion can be resumed
by enabling both DMA data transfer and conversion trigger.
For DAC channel1, an interrupt is also generated if its corresponding DMAUDRIE1 bit in the
DAC_CR register is enabled.
19.4.9 Noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVE1[1:0] to 01. The
preloaded value in LFSR is 0xAAA. This register is updated three dac_pclk clock cycles
after each trigger event, following a specific calculation algorithm.
RM0453 Rev 5
Digital-to-analog converter (DAC)
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