STMicroelectronics STM32WL5 Series Reference Manual page 370

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Reset and clock control (RCC)
Register
Offset
name
RCC_C2
AHB3ENR
0x150
Reset value
0x154
Reserved
RCC_C2
APB1ENR1
0x158
0
Reset value
RCC_C2
APB1ENR2
0x15C
Reset value
RCC_C2
APB2ENR
0x160
Reset value
RCC_C2
APB3ENR
0x164
Reset value
RCC_C2
AHB1SMENR
0x168
Reset value
RCC_C2
AHB2SMENR
0x16C
Reset value
RCC_C2
AHB3SMENR
0x170
Reset value
0x174
Reserved
RCC_
C2APB1SMENR1
0x178
1
Reset value
370/1450
Table 63. RCC register map and reset values (continued)
1
0
0
1
1
1
1
1
0
1
0
0
0
Reserved
0
0
0
0
0
1
1
1
Reserved
1
1
1
RM0453 Rev 5
0
0
0
0
0
0
0
1
1
1
1
RM0453
0
0
0
0
1
1
1
1
1
1
1

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