STMicroelectronics STM32WL5 Series Reference Manual page 419

RM0453
10.4.18 GPIOC bit set/reset register (GPIOC_BSRR)
Address offset: 0x0818
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13
rc_w1 rc_w1 rc_w1
15 14 13
BS15 BS14 BS13
rc_w1 rc_w1 rc_w1
Bits 31:29 BRy: Port PCy reset output data bit [y] in GPIOC_ODR (y = 15 to 13)
Note: If both BS0 and BR0 are set, BS0 has priority.
Bits 28:23 Reserved, must be kept at reset value.
Bits 22:16 BRy: Port PCy reset output data bit [y] in GPIOC_ODR (y = 6 to 0)
Bits 15:13 BSy: Port PCy set output data bit [y] in GPIOC_ODR (y = 15 to 13)
Note: If both BS0 and BR0 are set, BS0 has priority.
Bits 12:7 Reserved, must be kept at reset value.
Bits 6:0 BSy: Port PCy set output data bit [y] in GPIOC_ODR (y = 6 to 0)
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
These bits are read clear-write 1. A read to these bits returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
These bits are read clear-write 1. A read to these bits returns the value 0.
0: No action on the corresponding GPIOC_ODR.OD0
1: Resets the corresponding GPIOC_ODR.OD0.
24 23 22
Res. Res. BR6
rc_w1
8 7 6
Res. Res. BS6
rc_w1
RM0453 Rev 5
General-purpose I/Os (GPIO)
21 20 19 18
BR5 BR4 BR3 BR2
rc_w1 rc_w1 rc_w1 rc_w1
5 4 3 2
BS5 BS4 BS3 BS2
rc_w1 rc_w1 rc_w1 rc_w1
17 16
BR1 BR0
rc_w1 rc_w1
1 0
BS1 BS0
rc_w1 rc_w1
419/1450
431