STMicroelectronics STM32WL5 Series Reference Manual page 340

Reset and clock control (RCC)
7.4.27 RCC APB2 peripheral clock enable in Sleep mode register
(RCC_APB2SMENR)
Address offset: 0x080
Reset value: 0x0006 5A00
Access: word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART1 SPI1
Res. Res.
SMEN SMEN
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: Timer 17 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: TIM17 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: TIM17 clocks enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bit 17 TIM16SMEN: Timer 16 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: TIM16 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: TIM16 clock enabled by the clock gating during CPU1 CSleep mode, disabled during
CPU1 CStop mode
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: USART1 bus clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: USART1 bus clock enabled by the clock gating during CPU1 CSleep mode, disabled
during CPU1 CStop mode
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: SPI1 clock disabled by the clock gating during CPU1 CSleep and CStop modes
1: SPI1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1
CStop mode
Bit 11 TIM1SMEN: Timer 1 clock enable during CPU1 CSleep and CStop modes
This bit is set and cleared by software.
0: TIM1 clocks disabled by the clock gating during CPU1 CSleep and CStop modes
1: TIM1 clock enabled by the clock gating during CPU1 CSleep mode, disabled during CPU1
CStop mode
340/1450
28 27 26 25
Res. Res. Res.
12 11 10 9
TIM1 ADC
Res.
SMEN SMEN
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 5
21 20 19 18
TIM17
Res. Res. Res.
SMEN
rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
TIM16
Res.
SMEN
rw
1 0
Res. Res.