Figure 2. Memory Protection Example - STMicroelectronics STM32WL5 Series Reference Manual

Memory and bus architecture
A memory protection example with all different areas is given in
example. In this example the secure privileged hide protection area is only accessible read,
write, execute by the secure privileged bus masters when hide protection area access is
enabled in HDPADIS bit.
The secure privileged areas is only accessible read, write, execute by the secure privileged
bus masters.
The secure privileged write area is only accessible write by the secure privileged bus
masters, and read and execute by the privileged and unprivileged bus masters.
The secure unprivileged areas are accessible read, write, execute by the secure privileged
and unprivileged bus masters.
The non-secure unprivileged areas are accessible read write by the secure and non-secure
privileged and unprivileged bus masters, and are only accessible execute by the non-secure
privileged and unprivileged bus masters.
The secure bus masters are CPU2 and a secure DMA channel.
The non-secure bus masters are CPU1 and non-secure DMA channels.
HDPSA
TZSC_MPCWM0.UPWM1LGTH
TZSC_MPCWM0.UPWWM1LGTH
SFSA
Flash base address
TZSC_MPCWM1.UPWM1LGTH
SNBRSA
SRAM1 base address
68/1450

Figure 2. Memory protection example

Flash
Secure privileged hide
protection
Secure privileged
Secure unprivileged
read only
Secure unprivileged
Non-secure unprivileged
SRAM1
Secure privileged
Secure unprivileged
Non-secure unprivileged
RM0453 Rev 5
Figure 2: Memory protection
TZSC_MPCWM2.UPWM1LGTH
SBRSA
SRAM2 base address
RM0453
SRAM2
Secure privileged
Secure
unprivileged
Non-secure
unprivileged
MSv60756V2