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RM0453
Bit 2 CWUF3: Clear wake-up flag 3
Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0.
Bit 1 CWUF2: Clear wake-up flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0.
Bit 0 CWUF1: Clear wake-up flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0.
6.6.8
PWR control register 5 (PWR_CR5)
This register is not reset when exiting Standby modes.
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x01C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 SMPSEN: SMPS step-down converter enable
This bit enables the SMPS step-down converter.
0: SMPS step-down converter SMPS mode disabled (LDO mode enabled)
1: SMPS step-down converter SMPS mode enabled
Caution: Before enabling the SMPS, the SMPS clock detection must be enabled
Bit 14 RFEOLEN: sub-GHz radio end-of-life detector enable
0: Radio end-of-life detector disabled
1: Radio end-of-life detector enabled
Bits 13:0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
in SUBGHZ_SMPSC0R.CLKDE, if the application uses an external HSE clock
source (not coming from XO or TCXO but from another device).
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
Power control (PWR)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
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