STMicroelectronics STM32WL5 Series Reference Manual page 412

General-purpose I/Os (GPIO)
10.4.6 GPIOx output data register (GPIOx_ODR) (x = A to B)
Address offset: Block A: 0x0014
Address offset: Block B: 0x0414
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
OD15 OD14 OD13 OD12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODy: Port Pxy output data (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the
10.4.7 GPIOx bit set/reset register (GPIOx_BSRR) (x = A to B)
Address offset: Block A: 0x0018
Address offset: Block B: 0x0418
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13 BR12
rc_w1 rc_w1 rc_w1 rc_w1
15 14 13
BS15 BS14 BS13 BS12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 BRy: Port Pxy reset output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
Note: If both BSy and BRy are set, BSy has priority.
Bits 15:0 BSy: Port Pxy set output data bit [15:0] in GPIOx_ODR (y = 15 to 0)
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28 27 26 25
Res. Res. Res. Res.
12 11 10 9
OD11 OD10 OD9
rw rw rw rw
GPIOx_BSRR and GPIOx_BRR registers.
28 27 26 25
BR11 BR10 BR9
rc_w1 rc_w1 rc_w1
12 11 10 9
BS11 BS10 BS9
rc_w1 rc_w1 rc_w1
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Resets the corresponding GPIOx_ODR.OD[y] bit.
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit
1: Sets the corresponding GPIOx_ODR.OD[y] bit.
24 23 22
Res. Res. Res.
8 7 6
OD8 OD7 OD6
rw rw rw
24 23 22
BR8 BR7 BR6
rc_w1 rc_w1 rc_w1
8 7 6
BS8 BS7 BS6
rc_w1 rc_w1 rc_w1
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OD5 OD4 OD3 OD2
rw rw rw rw
21 20 19 18
BR5 BR4 BR3 BR2
rc_w1 rc_w1 rc_w1 rc_w1
5 4 3 2
BS5 BS4 BS3 BS2
rc_w1 rc_w1 rc_w1 rc_w1
RM0453
17 16
Res. Res.
1 0
OD1 OD0
rw rw
17 16
BR1 BR0
rc_w1 rc_w1
1 0
BS1 BS0
rc_w1 rc_w1