Table 226. I2C-Smbus Specification Data Setup And Hold Times - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
Note: t / t
AF(min)
device datasheet for t
The maximum t
mode, and Fast-mode Plus. It must be lower than the maximum of t
time. This maximum must only be met if the device does not stretch the LOW period (t
of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time
before it releases the clock.
The SDA rising edge is usually the worst case. In this case the previous equation becomes:
SDADEL ≤ {t
Note: This condition can be violated when NOSTRETCH = 0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to
•
After t
because the data was not yet written in I2C_TXDR register, SCL line is kept at low level
during the setup time. This setup time is
t
PRESC
To bridge the undefined region of the SDA transition (rising edge usually worst case), the
user must program SCLDEL in such a way that:
{[t + t
r (max)
Refer to
The SDA and SCL transition time values to use are the ones in the application. Using the
maximum values from the standard increases the constraints for the SDADEL and SCLDEL
calculation, but ensures the feature, whatever the application.
Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL
low during at least [(SDADEL + SCLDEL + 1) x (PRESC + 1) + 1] x t
transmission and reception modes. In transmission mode, if the data is not yet written in
I2C_TXDR when SDADEL counter is finished, the I2C keeps on stretching SCL low until the
next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH = 1 in slave mode, the SCL is not stretched. Consequently the SDADEL
must be programmed so that it guarantees a sufficient setup time.
Table 226. I
Symbol Parameter
t Data hold time
HD;DAT
t Data valid time
VD;DAT
t Data setup time
SU;DAT
Rise time of both
t
r
SDA and SCL signals
Fall time of both
t
f
SDA and SCL signals
1056/1450
are part of the equation only when the analog filter is enabled. Refer to the
AF(max)
values.
AF
can be, respectively, 3.45, 0.9, and 0.45 µs for Standard-mode, Fast-
HD;DAT
- t
VD;DAT (max) r (max)
Table 226 for t , t , t
f r HD;DAT
, or after sending SDA output when the slave had to stretch the clock
SDADEL
= (PRESC+ 1) x t
I2CCLK
] / [
(PRESC+ 1)] x t
SU;DAT (min)
Table 226 for t and t
r SU;DAT
2
C-SMBus specification data setup and hold times
Standard-mode
(Sm)
Min. Max
0
- 3.45
250
- 1000
- 300
- t - [(DNF + 4) x t
AF (max)
, and t standard values.
VD;DAT
t = (SCLDEL+ 1) x t
SCLDEL
impacts the setup time
. t
SCLDEL
]} - 1 ≤
SCLDEL
I2CCLK
standard values.
Fast-mode
(Fm)
Min. Max
- 0 -
- 0.9
- 100 -
- 300
- 300
RM0453 Rev 5
VD;DAT
]} / {(PRESC + 1) x t
I2CCLK
PRESC
t .
SU;DAT
I2CCLK
Fast-mode Plus
SMBus
(Fm+)
Min. Max Min.
0 - 0.3
- 0.45 -
50 - 250
- 120 -
- 120 -
RM0453
by a transition
)
LOW
}.
I2CCLK
, where
, in both
Unit
Max
-
µs
-
-
1000
ns
300