Figure 330. Rs232 Cts Flow Control - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
CTS
Transmit data register
TDR
TX
Note: For correct behavior, CTS must be deasserted at least 3 USART clock source periods
before the end of the current character. In addition it should be noted that the CTSCF flag
may not be set for pulses shorter than 2 x PCLK periods.
RS485 driver enable
The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register.
This enables the user to activate the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the
USART_CR1 control register. The deassertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bitfields in the USART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the USART_CR3 control register.
In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit time,
depending on the oversampling rate).
Universal synchronous/asynchronous receiver transmitter (USART/UART)

Figure 330. RS232 CTS flow control

Data 2 empty
Stop
Start
Data 1
bit
bit
Writing data 3 in TDR
RM0453 Rev 5
CTS
Data 3
Stop
Data 2
bit
Transmission of Data 3 is
delayed until CTS = 0
CTS
empty
Start
Idle
Data 3
bit
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