Table 65. Authorized Ahb Bus Master Ids - STMicroelectronics STM32WL5 Series Reference Manual

Hardware semaphore (HSEM)
–
Note: An interrupt does not lock the semaphore. After an interrupt, either the AHB bus master or
the process must still perform the lock procedure to lock the semaphore.
It is possible to have multiple AHB bus masters informed by the semaphore free interrupts.
Each AHB bus master gets its interrupt, and the first one to react locks the semaphore.
8.3.8 AHB bus master ID verification
The HSEM allows only authorized AHB bus master IDs to lock and unlock semaphores.
•
The AHB bus master 2-step lock write access to the semaphore HSEM_Rx register is
checked against the valid bus master IDs.
–
•
The AHB bus master 1-step lock read access from the semaphore HSEM_RLRx
register is checked against the valid bus master IDs.
–
•
The semaphore unlock write access to the HSEM_CR register is checked against the
valid bus master IDs. Only the valid bus master IDs can write to the HSEM_CR register
and unlock any of the COREID semaphores.
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Table 65
Note: Accesses from unauthorized AHB bus master IDs to other registers are granted.
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If the semaphore lock fails, wait for semaphore free interrupt.
Accesses from unauthorized AHB bus master IDs are discarded and do not lock
the semaphore.
An unauthorized AHB bus master ID read from HSEM_RLRx returns all 0.
Accesses from unauthorized AHB bus master IDs are discarded and do not clear
the COREID semaphores.
details the relation between bus master/processor and COREID.

Table 65. Authorized AHB bus master IDs

Bus master 0 (processor1)
COREID = 4
RM0453 Rev 5
Bus master 1 (processor2)
COREID = 8
RM0453