STMicroelectronics STM32WL5 Series Reference Manual page 360

Reset and clock control (RCC)
7.4.42 RCC CPU2 AHB3 peripheral clock enable in Sleep mode register
(RCC_C2AHB3SMENR)
Address offset: 0x170
Reset value: 0x0387 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHSMEN: Flash memory interface clock enable during CPU2 CSleep and CStop modes
Bit 24 SRAM2SMEN: SRAM2 interface clock enable during CPU2 CSleep and CStop modes
Bit 23 SRAM1SMEN: SRAM1 interface clock enable during CPU2 CSleep and CStop modes
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN: True RNG clock enable during CPU2 CSleep and CSleep and CStop modes
360/1450
28 27 26 25
FLASH
Res. Res. Res.
SMEN
rw
12 11 10 9
Res. Res. Res. Res.
This bit is set and cleared by software.
0: Flash memory interface clock disabled by the clock gating during CPU2 CSleep and
CStop modes
1: Flash memory interface clock enabled by the clock gating during CPU2 CSleep mode,
disabled during CPU2 CStop mode.
This bit is set and cleared by software.
0: SRAM2 clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: SRAM2 clock enabled by the clock gating during CPU2 CSleep mode, disabled during
CPU2 CStop mode
This bit is set and cleared by software.
0: SRAM1 interface clock disabled by the clock gating during CPU2 CSleep and CStop
modes
1: SRAM1 interface clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
This bit is set and cleared by software.
0: True RNG bus clock disabled by the clock gating during CPU2 CSleep and CStop modes
1: True RNG bus clock enabled by the clock gating during CPU2 CSleep mode, disabled
during CPU2 CStop mode
24 23 22
SRAM2 SRAM1
Res.
SMEN SMEN
rw rw
8 7 6
Res. Res. Res.
RM0453 Rev 5
21 20 19 18
RNG
Res. Res. Res.
SMEN
rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
AES PKA
SMEN SMEN
rw rw
1 0
Res. Res.