STMicroelectronics STM32WL5 Series Reference Manual page 645

RM0453
Bit 2 SECS: Seed error current status
Bit 1 CECS: Clock error current status
Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.
Bit 0 DRDY: Data ready
Note: The DRDY bit can rise when the peripheral is disabled (RNGEN = 0 in the RNG_CR
22.7.3 RNG data register (RNG_DR)
Address offset: 0x008
Reset value: 0x0000 0000
The RNG_DR register is a read-only register that delivers a 32-bit random value when read.
The content of this register is valid when the DRDY = 1 and the value is not 0x0, even if
RNGEN = 0.
31 30 29
r r r
15 14 13
r r r
Bits 31:0 RNDATA[31:0]: Random data
0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a
faulty sequence was detected and the situation has been recovered.
1: At least one of the following faulty sequences has been detected:
– Runtime repetition count test failed (noise source has provided more than 24
consecutive bits at a constant value 0 or 1, or more than 32 consecutive occurrence
of two bits patterns 01 or 10)
– Startup or continuous adaptive proportion test on noise source failed.
– Startup post-processing/conditioning sanity check failed.
0: The RNG clock is correct (f
slow clock was detected and the situation has been recovered.
1: The RNG clock is too slow (f
0: The RNG_DR register is not yet valid, no random data is available.
1: The RNG_DR register contains valid random data.
Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns
to 0 until a new random value is generated.
register).
If IE=1 in the RNG_CR register, an interrupt is generated when DRDY = 1.
28 27 26 25
r r r r
12 11 10 9
r r r r
32-bit random data, which are valid when DRDY = 1. When DRDY = 0, the RNDATA value
is zero.
When DRDY is set,
it is recommended to always verify that RNG_DR is different from
zero. Because when it is the case a seed error occurred between RNG_SR polling and
RND_DR output reading (rare event).
True random number generator (RNG)
> f /32). If the CEIS bit is set, this means that a
RNGCLK HCLK
< f /32).
RNGCLK HCLK
24 23 22
RNDATA[31:16]
r r r
8 7 6
RNDATA[15:0]
r r r
RM0453 Rev 5
21 20 19 18
r r r r
5 4 3 2
r r r r
17 16
r r
1 0
r r
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