Figure 354. Data Clock Timing Diagram - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Figure 354, shows an SPI full-duplex transfer with the four combinations of the CPHA and
CPOL bits.
Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
CPOL = 1
CPOL = 0
NSS (to slave)
Capture strobe
CPOL = 1
CPOL = 0
NSS (to slave)
Capture strobe
1. The order of data bits depends on LSBFIRST bit setting.
Data frame format
The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the
value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set
from 4-bit up to 16-bit length and the setting applies for both transmission and reception.
Whatever the selected data frame size, read access to the FIFO must be aligned with the
FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned
into either a byte (if the data fits into a byte) or a half-word (see
communication, only bits within the data frame are clocked and transferred.
Serial peripheral interface / integrated interchip sound (SPI/I2S)

Figure 354. Data clock timing diagram

(1)
MSBit
MOSI
(1)
MISO
MSBit
(1)
MOSI MSBit
(1)
MISO MSBit
CPHA =1
CPHA =0
RM0453 Rev 5
LSBit
LSBit
LSBit
LSBit
Figure 355). During
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