Power control (PWR)
Bit 11 WRFBUSYF: Radio busy wake-up flag
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 WPVDF: Wake-up PVD flag
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 WUF3: Wake-up flag 3
Bit 1 WUF2: Wake-up flag 2
Bit 0 WUF1: Wake-up flag 1
6.6.6
Power status register 2 (PWR_SR2)
This register is partially reset when exiting Standby/Shutdown modes.
Address offset: 0x014
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
PVMO3
Res.
Res.
r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 PVMO3: Peripheral voltage monitoring output: V
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 PVDO: Programmable voltage detector output
270/1450
This bit is set when a wake-up event is detected on radio busy. It is cleared by writing '1' in
the CWRFBUSYF bit of the PWR_SCR register.
This bit is set when a wake-up event is detected on PVD. It is cleared by writing '1' in the
CWPVDF bit of the PWR_SCR register.
This bit is set when a wake-up event is detected on wake-up pin, WKUP3. It is cleared by
writing 1 in the CWUF3 bit of the
This bit is set when a wake-up event is detected on wake-up pin, WKUP2. It is cleared by
writing 1 in the CWUF2 bit of the
This bit is set when a wake-up event is detected on wake-up pin, WKUP1. It is cleared by
writing 1 in the CWUF1 bit of the
28
27
26
25
Res.
Res.
Res.
12
11
10
9
PVDO
VOSF
r
r
r
0: V
voltage above PVM3 threshold (around 1.62 V)
DDA
1: V
voltage below PVM3 threshold (around 1.62 V)
DDA
PVM3 output is valid after the PVM3 wake-up time.
0: V
or voltage level on PVD_IN above the selected PVD threshold
DD
1: V
or voltage level on PVD_IN below the selected PVD threshold
DD
PWR status clear register
PWR status clear register
PWR status clear register
24
23
22
Res.
Res.
Res.
8
7
6
r
r
r
DDA
RM0453 Rev 5
(PWR_SCR).
(PWR_SCR).
(PWR_SCR).
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
r
r
r
r
versus 1.62 V
RM0453
17
16
Res.
Res.
1
0
r
r
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