STMicroelectronics STM32WL5 Series Reference Manual page 67

RM0453
The memory protection allows the following areas to be defined within a memory:
•
When memory unprivileged address offset > secure address offset
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–
–
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Or
•
When memory security address offset > unprivileged address offset
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–
–
–
For more information see
Further more a hide protection area can be defined in the flash memory by the hide
protection area address offset defined in HDPSA user option.
When enabled, the flash memory area starting from the HDPSA address offset up to the end
of the flash memory is hide protected. This means that the area is accessible from device
reset or wake up from Standby mode, and can be protected from any access by disabling
the hide protection area with the HDPADIS bit in flash memory access control register 2
(FLASF_ACR2).
Memory protection is controlled by the parameters as listed below:
•
Flash memory security address offset is defined in SFSA user option.
The unprivileged watermark address offset is defined in
GTZC_TZSC_MPCWM0.UPWM1LGTH and the privileged and unprivileged, read and
execute watermark in address offset defined in
GTZC_TZSC_MPCWM0.UPWWM1LGTH.
–
•
SRAM1 security address offset is defined in SNBRSA user option.
The unprivileged watermark address offset is defined in
GTZC_TZSC_MPCWM1.UPWM1LGTH.
–
•
SRAM2 security address offset is defined in SBRSA user option
The unprivileged watermark address offset is defined in
GTZC_TZSC_MPCWM2.UPWM1LGTH.
–
When enabled, the memory area starting from the security address offset up to the end of
the memory is secure.
When enabled, the unprivileged area starts from the memory base address up to the
watermark address offset, and the area above the watermark up to the end of the memory is
privileged.
Secure privileged
Flash memory only: secure privileged and unprivileged read execute only (non
base thread mode)
Secure unprivileged
Non-secure unprivileged
Secure privileged
Flash memory only: non-secure privileged and unprivileged read execute only
(non base thread mode)
Non-secure privileged
Non-secure unprivileged
Section 3.1: GTZC
Flash memory privileged is only available when the flash memory is secure
(ESE = 1).
SRAM1 security is optional and privilege can be enabled without having security.
SRAM2 security is optional and privilege can be enabled without having security.
introduction.
RM0453 Rev 5
Memory and bus architecture
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