Table 88. Dmamux Register Map And Reset Values - STMicroelectronics STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
14.6.7
DMAMUX register map
The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.
Offset
Register
DMAMUX_C0CR
0x000
Reset value
DMAMUX_C1CR
0x004
Reset value
DMAMUX_C2CR
0x008
Reset value
DMAMUX_C3CR
0x00C
Reset value
DMAMUX_C4CR
0x010
Reset value
DMAMUX_C5CR
0x014
Reset value
DMAMUX_C6CR
0x018
Reset value
DMAMUX_C7CR
0x01C
Reset value
DMAMUX_C8CR
0x020
Reset value
DMAMUX_C9CR
0x024
Reset value
DMAMUX_C10CR
0x028
Reset value
DMAMUX_C11CR
0x02C
Reset value
DMAMUX_C12CR
0x030
Reset value
DMAMUX_C13CR
0x034
Reset value
0x038 -
Reserved
0x07C
DMAMUX_CSR
0x080
Reset value
DMAMUX_CCFR
0x084
Reset value

Table 88. DMAMUX register map and reset values

SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
SYNC_ID[4:0]
NBREQ[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0
RM0453 Rev 5
DMA request multiplexer (DMAMUX)
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
DMAREQ_ID[6:0]
0 0 0 0 0 0 0
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