Figure 318. Usart Example Of Synchronous Master Transmission; Figure 319. Usart Data Clock Timing Diagram In Synchronous Master Mode; (M Bits = 00) - STMicroelectronics STM32WL5 Series Reference Manual

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Note: In master mode, the CK pin operates in conjunction with the TX pin. Thus, the clock is
provided only if the transmitter is enabled (TE = 1) and data are being transmitted
(USART_TDR data register written). This means that it is not possible to receive
synchronous data without transmitting data.

Figure 319. USART data clock timing diagram in synchronous master mode

Idle or preceding
transmission
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data on TX
(from master)
Data on RX
(from slave)
Capture strobe
1144/1450

Figure 318. USART example of synchronous master transmission

USART
Start
0
LSB
Start
0
LSB
RX
TX
CK

(M bits = 00)

M bits = 00 (8 data bits)
1 2 3 4
1 2 3 4
RM0453 Rev 5
Data out
Data in
Synchronous device
(slave SPI)
Clock
Stop
*
*
*
*
5 6 7
MSB Stop
5 6 7
MSB
*
*LBCL bit controls last data pulse
RM0453
MSv31158V2
Idle or next
transmission
MSv34709V2