Table 133. Aes Internal Input/Output Signals; Figure 101. Aes Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

AES hardware accelerator (AES)
23.3 AES implementation
The devices have one AES peripheral.
23.4 AES functional description
23.4.1 AES block diagram
Figure 101
32-bit
AHB bus
aes_hclk
aes_in_dma
aes_out_dma
23.4.2 AES internal signals
Table 133
Signal name
aes_hclk
aes_it
aes_in_dma
aes_out_dma
648/1450
shows the block diagram of AES.

Figure 101. AES block diagram

AES
AHB
interface
DMA
interface
IRQ
aes_it
interface
describes the user relevant internal signals interfacing the AES peripheral.

Table 133. AES internal input/output signals

Signal type
Input
Output
Input/Output
Input/Output
32-bit
Banked registers
access
AES_KEYRx
key
AES_IVRx
IV, counter
AES_SR
status
control AES_CR
AES_DINR
data in
AES_DOUTR
data out
AES_SUSPRx
Control Logic
AHB bus clock
AES interrupt request
Input DMA single request/acknowledge
Output DMA single request/acknowledge
RM0453 Rev 5
KEY
IVI
swap
AES
DIN Core
(AEA)
DOUT
Save / Restore
Description
RM0453
MSv42154V1