STMicroelectronics STM32WL5 Series Reference Manual page 574

Analog-to-digital converter (ADC)
18.12.3 ADC control register (ADC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
ADVR
ADCAL Res. Res.
EGEN
rs rw
15 14 13 12
Res. Res. Res. Res.
Bit 31 ADCAL: ADC calibration
This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0).
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 ADVREGEN: ADC Voltage Regulator Enable
This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output
is available after t
It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0.
0: ADC voltage regulator disabled
1: ADC voltage regulator enabled
Note: The software is allowed to program this bit field only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 27:5 Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to
accept a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to '1' is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.
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27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
.
ADCVREG_STUP
RM0453 Rev 5
23 22 21
Res. Res. Res. Res.
7 6 5
Res. Res. Res. ADSTP
RM0453
20 19 18 17
Res. Res. Res.
4 3 2 1
ADSTA
Res. ADDIS
RT
rs rs rs
16
Res.
0
ADEN
rs