Table 132. Rng Register Map And Reset Map - STMicroelectronics STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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True random number generator (RNG)
22.7.4
RNG health test control register (RNG_HTCR)
Address offset: 0x010
Reset value: 0x0000 5A4E
Writing in RNG_HTCR is taken into account only if the CONDRST bit is set, and the
CONFIGLOCK bit is cleared in the RNG_CR. Writing to this register is ignored if
CONFIGLOCK=1.
31
30
29
rw
rw
rw
15
14
13
rw
rw
rw
Bits 31:0 HTCFG[31:0]: health test configuration
Note: The RNG behavior, including the read to this register, is not guaranteed if a different
22.7.5
RNG register map
Offset Register name
RNG_CR
0x000
Reset value
RNG_SR
0x004
Reset value
RNG_DR
0x008
Reset value
RNG_HTCR
0x010
Reset value
Refer to
646/1450
28
27
26
25
rw
rw
rw
rw
12
11
10
9
rw
rw
rw
rw
This configuration is used by RNG to configure the health tests. See
entropy source validation
value from the recommended value is written.
When reading or writing this register magic number; 0x17590ABC must be written
immediately before to the RNG_HTCR register.

Table 132. RNG register map and reset map

RNG_CONFIG1[5:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 2.6
for the register boundary addresses.
24
23
22
HTCFG[31:16]
rw
rw
rw
8
7
6
HTCFG[15:0]
rw
rw
rw
for the recommended value.
RNG_
.CLKDIV
CONFIG2
[3:0]
1
0
0
0
0
0
0
0
0
RNDATA[31:0]
0
0
0
0
0
0
0
0
0
HTCFG[31:0]
0
0
0
0
1
1
0
0
0
RM0453 Rev 5
21
20
19
rw
rw
rw
5
4
3
rw
rw
rw
Section 22.6: RNG
RNG_
CONFIG3
[2:0]
[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
RM0453
18
17
16
rw
rw
rw
2
1
0
rw
rw
rw
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0

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