STMicroelectronics STM32WL5 Series Reference Manual page 520

Extended interrupts and event controller (EXTI)
16.6.8 EXTI pending register (EXTI_PR2)
Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. PIF45 Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PIF45: pending bit on event input 45
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 PIF41: pending bit on event input 41
Bit 8 PIF40: pending bit on event input 40
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PIF34: pending bit on event input 34
Bits 1:0 Reserved, must be kept at reset value.
16.6.9 EXTI interrupt mask register (EXTI_CnIMR1)
Address offset: Block 1: 0x080
Address offset: Block 2: 0x0C0
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 IM[31:0]: Wake-up with interrupt mask on event input x (x= 31 to 0)
520/1450
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. PIF41
rw
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
For each bit of this field:
0: Wake-up with interrupt request from line x is masked.
1: Wake-up with Interrupt request from line x is unmasked.
24 23 22
Res. Res. Res.
8 7 6
PIF40 Res. Res.
rw
24 23 22
IM[31:16]
rw rw rw
8 7 6
IM[15:0]
rw rw rw
RM0453 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. PIF34
rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
Res. Res.
17 16
rw rw
1 0
rw rw