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AES hardware accelerator (AES)
Offset
Register
AES_SUSP1R
0x044
Reset value
0
AES_SUSP2R
0x048
Reset value
0
AES_SUSP3R
0x04C
Reset value
0
AES_SUSP4R
0x050
Reset value
0
AES_SUSP5R
0x054
Reset value
0
AES_SUSP6R
0x058
Reset value
0
AES_SUSP7R
0x05C
Reset value
0
0x060-
Reserved
0x3FF
Refer to
694/1450
Table 142. AES register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Section 2.6 on page 71
SUSP[31:0]
0
0
0
0
0
0
0
0
0
SUSP[31:0]
0
0
0
0
0
0
0
0
0
SUSP[31:0]
0
0
0
0
0
0
0
0
0
SUSP[31:0]
0
0
0
0
0
0
0
0
0
SUSP[31:0]
0
0
0
0
0
0
0
0
0
SUSP[31:0]
0
0
0
0
0
0
0
0
0
SUSP[31:0]
0
0
0
0
0
0
0
0
0
for the register boundary addresses.
RM0453 Rev 5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0453
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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