STMicroelectronics STM32WL5 Series Reference Manual page 656

AES hardware accelerator (AES)
Data append using interrupt
The method uses interrupt from the AES peripheral to control the data append, through the
following sequence:
1. Enable interrupts from AES by setting the CCFIE bit of the AES_CR register.
2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. Write first four input data words into the AES_DINR register.
4. Handle the data in the AES interrupt service routine, upon interrupt:
a)
b)
c)
d)
e)
Note: AES is tolerant of delays between consecutive read or write operations, which allows, for
example, an interrupt from another peripheral to be served between two AES computations.
NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.
Data append using DMA
With this method, all the transfers and processing are managed by DMA and AES. To use
the method, proceed as follows:
1. Prepare the last four-word data block (if the data to process does not fill it completely),
by padding the remainder of the block with zeros.
2. Configure the DMA controller so as to transfer the data to process from the memory to
the AES peripheral input and the processed data from the AES peripheral output to the
memory, as described in
controller so as to generate an interrupt on transfer completion. In case of GCM
payload encryption or CCM payload decryption, DMA transfer must not include the
last four-word block if padded with zeros. The sequence described in
through polling
setup before processing the block, for AES to compute a correct tag.
3. Enable the AES peripheral by setting the EN bit of the AES_CR register
4. Enable DMA requests by setting the DMAINEN and DMAOUTEN bits of the AES_CR
register.
5. Upon DMA interrupt indicating the transfer completion, get the AES-processed data
from the memory.
Note: The CCF flag has no use with this method, because the reading of the AES_DOUTR
register is managed by DMA automatically, without any software action, at the end of the
computation phase.
NPBLB bits are not used in header phase of GCM, GMAC, and CCM chaining modes.
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Read four output data words from the AES_DOUTR register.
Clear the CCF flag and thus the pending interrupt, by setting the CCFC bit of the
AES_CR register.
If the data block just processed is the second-last block of an message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros and, in case of GCM payload encryption or
CCM payload decryption, specify the number of non-valid bytes, using the NPBLB
bitfield of the AES_CR register, for AES to compute a correct tag;. Then proceed
with point 4e).
If the data block just processed is the last block of the message, discard the data
that is not part of the data, then disable the AES peripheral by clearing the EN bit
of the AES_CR register and quit the interrupt service routine.
Write next four input data words into the AES_DINR register and quit the interrupt
service routine.
Section 23.4.16: AES DMA
must be used instead for this last block, because NPBLB bits must be
RM0453 Rev 5
interface. Configure the DMA
Data append
RM0453