Clock Security System On Lse (Lsecss); Spi2S2 Clock; Sub-Ghz Radio Spi Clock; Table 59. Spi2S2 I2S Clock Pll Configurations - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
7.2.11

Clock security system on LSE (LSECSS)

A CSS on LSE can be activated by software writing the LSECSSON bit in the
domain control register
RTC software reset, or after a failure detection on LSE. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION) and ready (LSERDY and LSIRDY set by
hardware), and after the RTC clock has been selected by RTCSEL. The LSI clock is
automatically enabled.The LSE must not be disabled with the LSEON bit when LSECSS is
enabled with the LSECSSON bit.
The CSS on LSE is working in all modes except VBAT. It is working also under system reset
(excluding power on reset). If a failure is detected on the external 32 kHz oscillator, the LSE
clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
MSI was in PLL-mode, this mode is disabled.
In Standby mode, a wake-up is generated. In other modes an interrupt can be sent to wake-
up the software (see
flag register
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator
(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE32, with
RTCSEL), or take any required action to secure the application.
7.2.12

SPI2S2 clock

The SPI2S2 I2S clock is derived from the HSI16 clock, PLL output, or from the external
I2S_CLK signal. It can reach 48 MHz.
The serial audio interface requires either a frequency close to 49.152 MHz or 11.2896 MHz.
The 49.152 MHz aims to derive audio sampling frequencies of 192 kHz, 96 kHz, 48 kHz,
32 kHz, 16 kHz and 8 kHz. While 11.2896 MHz targets audio sampling frequencies of
44.1 kHz, 22.05 kHz and 11.025 kHz. The targeted worts case accuracy must be 0.05 %.
Possible clock configurations are given in the table below.
Clock source
MSI (4 MHz)
HSE32 (32 MHz)
HSI16 (16 MHz)
MSI (4 MHz)
HSE32 (32 MHz)
HSI16 (16 MHz)
7.2.13

Sub-GHz radio SPI clock

The sub-GHz radio SPI clock is derived from the PCLK3 clock. The SUBGHZSPI_SCK
frequency is obtained by PCLK3 divided by two. The SUBGHZSPI_SCK clock maximum
speed must not exceed 16 MHz.
(RCC_BDCR). This bit can be disabled only by a hardware reset or
RCC clock interrupt enable register
(RCC_CIFR), RCC clock interrupt clear register

Table 59. SPI2S2 I2S clock PLL configurations

M
1
7
2
1
3
1
RM0453 Rev 5
(RCC_CIER),
PLLN PLLQ
4 7
43 4
43 7
79 28
18 17
12 17
Reset and clock control (RCC)
RCC backup
RCC clock interrupt
(RCC_CICR)).
I2C clock frequency
49.14286 MHz (-0.019%)
11.28571 MHz (0.034%)
11.29412 MHz (0.040%)
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