Table 223. I2C Input/Output Pins; Table 224. I2C Internal Input/Output Signals - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
34.4.2 I2C pins and internal signals
Pin name
I2C_SDA
I2C_SCL
I2C_SMBA
Internal signal name
i2c_ker_ck
i2c_pclk
i2c_it
i2c_rx_dma
i2c_tx_dma
34.4.3 I2C clock requirements
The I2C kernel is clocked by I2CCLK.
The I2CCLK period t
• t
I2CCLK
•
t
I2CCLK
with:
t : SCL low time and t
LOW
t : when enabled, sum of the delays brought by the analog and by the digital filters.
filters
The digital filter delay is DNF x t
The PCLK clock period t
•
t
PCLK
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for t
34.4.4 Mode selection
The interface can operate in one of the four following modes:
•
Slave transmitter
•
Slave receiver
•
Master transmitter
•
Master receiver
1052/1450

Table 223. I2C input/output pins

Signal type
Bidirectional
Bidirectional
Bidirectional

Table 224. I2C internal input/output signals

Signal type
Input
Input
Output
Output
Output
must respect the following conditions:
I2CCLK
< (t - t ) / 4
LOW filters
< t
HIGH
: SCL high time
HIGH
I2CCLK
must respect the condition:
PCLK
< 4 / 3 t (t : SCL period)
SCL SCL
I2C data
I2C clock
SMBus alert
I2C kernel clock, also named I2CCLK in this document
I2C APB clock
I2C interrupts, refer to
interrupt sources
I2C receive data DMA request (I2C_RX)
I2C transmit data DMA request (I2C_TX)
.
RM0453 Rev 5
Description
Description
Table 237 for the full list of
RM0453
.
I2CCLK