Table 15. Errors In Page-Based Row Programming - STMicroelectronics STM32WL5 Series Reference Manual

Embedded flash memory (FLASH)
If an error occurs during a program or erase operation, one of the following error flags is set
in FLASH_SR and FLASH_C2SR:
•
PROGERR, SIZERR, PGAERR, PGSERR, MISSERR (program error flags)
•
WRPERR (protection error flag)
In this case, if the error interrupt enable bit ERRIE is set in FLASH_CR or FLASH_C2CR, an
interrupt is generated and the operation error flag OPERR is set in FLASH_SR and
FLASH_C2SR.
Note: If several successive errors are detected (for example, in case of DMA transfer to the flash
memory), the error flags cannot be cleared until the end of the successive write request.
PGSERR and PGAERR in a page-based row programming
In case of fast programming, the table below describes how PGAERR and PGSERR are
handled.
Last page/row
page [x]/row [y]
After a system reset, no MER or PER is performed. Any programming attempt causes a
PGAERR and a PGSERR.
Programming errors causing a bus error
The error conditions listed below do not generate an error flag but a bus error instead:
•
AHB write to any page when RDP level 1 and boot is performed from the system flash
memory or SRAM1
•
AHB write when the flash memory is powered down
•
Read or write from the flash memory through the debugger
•
Read from the flash memory when fast row programming is ongoing, for the source
which requested the fast row programming
• New programming request when the previous one is not finished
•
FLASH_CR register write between the two accesses of a double-word programming
• FLASH_CR register write when PESD is active (set)
•
Write a wrong key in FLASH_KEYR or FLASH_OPTKEYR register
•
Any subsequent write to FLASH_KEYR or FLASH_OPTKEYR after unlocking the
respective feature
Programming and caches
If a flash memory write access impacts data in the data cache, the flash memory write
access modifies the data in the memory and in the cache.
If an erase operation in the flash memory also concerns data in the data cache or instruction
cache, the user must ensure that these data are rewritten before they are accessed during
code execution. Upon an erase operation, the cache content is invalidated.
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Table 15. Errors in page-based row programming

Current page/row
page [x] / row [x-n]
page [x-n] / row [any]
page [x+n] / row [any]
RM0453 Rev 5
MER active
PGAERR
PGAERR & PGSERR
No error
RM0453
PPER active
PGAERR
PGAERR & PGSERR
PGSERR