Figure 290. Master Initialization Flow; Figure 291. 10-Bit Address Read Access With Head10R = 0 - STMicroelectronics STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
Note: The START bit is reset by hardware when the slave address is sent on the bus, whatever
the received acknowledge value. The START bit is also reset by hardware if an arbitration
loss occurs.
In 10-bit addressing mode, when the slave address first 7 bits are NACKed by the slave, the
master re-launches automatically the slave address transmission until ACK is received. In
this case ADDRCF must be set if a NACK is received from the slave, in order to stop
sending the slave address.
If the I2C is addressed as a slave (ADDR = 1) while the START bit is set, the I2C switches to
slave mode and the START bit is cleared.
Note: The same procedure is applied for a repeated start condition. In this case BUSY = 1.
Initialization of a master receiver addressing a 10-bit address slave
•
If the slave address is in 10-bit format, the user can choose to send the complete read
sequence by clearing the HEAD10R bit in the I2C_CR2 register. In this case the master
automatically sends the following complete sequence after the START bit is set:
(Re)Start + Slave address 10-bit header Write + Slave address second byte + REStart
+ Slave address 10-bit header Read
1 1 1 1 0 X X
Slave address
S
1st 7 bits
1072/1450

Figure 290. Master initialization flow

Enable interrupts and/or DMA in I2C_CR1

Figure 291. 10-bit address read access with HEAD10R = 0

0
Slave address
R/W A1
2nd byte
Write
RM0453 Rev 5
Master
initialization
Initial settings
End
1 1 1 1 0 X X 1
Slave address
A2 Sr R/W
1st 7 bits
Read
RM0453
MS19859V2
A3 DATA A DATA
MSv41066V1
A P