Figure 382. Audio Sampling Frequency Definition; Figure 383. I S Clock Generator Architecture - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
The appropriate transition is a falling edge on WS signal when I
or a rising edge for other standards. The falling edge is detected by sampling first WS to 1
and then to 0, and vice-versa for the rising edge detection.
If ASTRTEN = 1, the user has to enable the audio interface before the WS becomes active.
This means that the I2SE bit must be set to 1 when WS = 1 for I
WS = 0 for other standards.
37.7.4 Clock generator
2
The I S bit rate determines the data flow on the I
frequency.
2
I S bit rate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I
2
I S bit rate = 16 × 2 × f
2
It is: I S bit rate = 32 x 2 x f
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
I²SxCLK
1. Where x can be 2 or 3.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
S
if the packet length is 32-bit wide.
S

Figure 382. Audio sampling frequency definition

16-or 32-bit left
sampling point
F : audio sampling frequency
S
Figure 383. I
8-bit linear divider
+ reshaping stage
I²SDIV[7:0]
MCKOE ODD
2
S data line and the I
2
S bit rate is calculated as follows:
16-or 32-bit
right channel
channel
32- or 64-bits
F
S
2
S clock generator architecture
Divider by 4
RM0453 Rev 5
2
S Philips Standard is used,
2
S Philips standard, or when
2
S clock signal
sampling point
0
0
Div2
1
1
MCKOE
MS30108V1
MCK
CK
MS30109V1
1291/1450
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