Figure 40. Ipcc Half-Duplex Channel Mode Transfer Timing; Figure 41. Ipcc Half-Duplex - Send Procedure State Diagram - STMicroelectronics STM32WL5 Series Reference Manual

RM0453
Once the processor A retrieves the response from the memory, it does not change the
channel status flags. The memory location access is kept by processor A for the next
communication data.

Figure 40. IPCC Half-duplex channel mode transfer timing

Processor A
CHnF
TX free interrupt
Processor B
RX occupied interrupt
Memory occupation

Figure 41. IPCC Half-duplex - Send procedure state diagram

Communication processor A
Send
Communication data
Complete communication posted Write response pending = 1
Write
Communication
data
Read
Communication
data
Communication data
Wait for
Response read
Response pending = 1
Response pending = 0
Write
Communication
data to Memory
Set Channel N
occupied
Write CHnS (set CHnF = 1)
UNMASK
Channel N
free interrupt
Write CHnFM = 0
End
RM0453 Rev 5
Inter-processor communication controller (IPCC)
Read
Communication
Response
Write
Response
Response
Response processor B
Response pending = 1
Complete communication posted
Write
data
Read
Communication
Response
data
Communication data
Write Response
to Memory
Write response pending = 0
Clear Channel N free
Write CHnC (set CHnF = 0)
UNMASK
Channel N
occupied interrupt
Write CHnOM = 0
Write
Response
MS42435V1
End
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