RM0453
19.7.13
DAC register map
Table 119
Register
Offset
name
reset value
DAC_CR
0x00
Reset value
DAC_
SWTRGR
0x04
Reset value
DAC_
DHR12R1
0x08
Reset value
DAC_
DHR12L1
0x0C
Reset value
DAC_
DHR8R1
0x10
Reset value
0x14 -
Reserved
0x1C
0x20 -
Reserved
0x28
DAC_
DOR1
0x2C
Reset value
0x30
Reserved
DAC_SR
0x34
Reset value
DAC_CCR
0x38
Reset value
DAC_MCR
0x3C
Reset value
DAC_
SHSR1
0x40
Reset value
0x44
Reserved
DAC_
SHHR
0x48
Reset value
summarizes the DAC registers.
Table 119. DAC register map and reset values
Res.
0
0
0
Res.
Res.
Res.
0
0
Res.
RM0453 Rev 5
Digital-to-analog converter (DAC)
TSEL1[3:1]
0
0
0
0
0
0
0
0
DACC1DHR[11:0]
0
0
0
0
0
0
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
DACC1DHR[7:0]
0
0
DACC1DOR[11:0]
0
0
0
0
0
0
0
TSAMPLE1[9:0]
0
0
0
0
THOLD1[9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
MODE1
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
615/1450
616
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